The present invention relates to the testing of integrated non-linear circuits, and more particularly, it relates to testing of the AC parameters of such circuits. Functional testing of the DC parameters of large scale integrated circuits is well developed in the art. In such functional testing, the integrated circuits are tested in order to determine the ability of the integrated circuit to fulfill the basic functions for which they were designed. These DC functional tests include tests for switching thresholds, saturation levels, the size of the load which the circuit is capable of driving and the immunity of the circuit to noise.
Such DC functional tests are usually performed directly on the integrated circuit chip or a computer simulation of the chip by applying to specific input points or contact terminals of the integrated circuit chip a DC signal pattern and monitoring a resulting DC pattern at output points or other terminals on the integrated circuit chip. In such DC testing, the test pattern is a bilevel input electrical signal pattern made up of a plurality of pattern increments, in sequence, each increment comprising a plurality of parallel bilevel signals corresponding to the plurality of input points in the circuit to be tested. A corresponding resulting output signal is sensed at the plurality of output points in the circuit being tested.
Suitable methods and apparatus for automatically generating such test patterns for testing the DC functional parameters of complex non-linear integrated circuits are known in the art. Copending application Ser. No. 825,870, filed May 19, 1969, for a "Logic Test System", assigned to the same assignee of the present application, describes a method and apparatus for generating a highly rapid sequence of randomly varying or pseudo-randomly varying DC bilevel pattern increments for testing complex integrated circuits.
While DC functional testing of complex integrated circuits has been extensively implemented in the semiconductor circuit field, the testing of AC parameters, which includes such factors as rise time, fall time and circuit delays, has been in relatively limited usage, particularly in the case of large scale integrated circuits. One reason appears to be the scarcity of systems for the generation or composition of AC test patterns for integrated circuits by wholly automated or partially automated methods. On the other hand, while simple test patterns for AC parameters for relatively simple integrated circuits may be composed manually, in the case of the more complex large scale integrated circuits, manual composition of AC test patterns becomes an exceedingly difficult, costly and lengthy task.